In fabricating a vertical, bipolar transistor, it is generally desirable to minimize the device collector-base capacitance, C.sub.cb (i.e. the capacitance between the adjoining base and collector regions) Such capacitance typically has the undesirable affect of decreasing device switching speed, and increasing the device switching voltages. It is further desirable to minimize the device base-width, narrow basewidth devices typically exhibiting improved performance.
One method of minimizing the undesirable collector-base capacitance is to minimize the P-N junction area between the device base and collector regions. Along the same lines, this capacitance C.sub.cb also decreases as the distance between the base contact and the device collector region is increased. These goals, however, typically conflict with the requirement to make a reliable, low resistance electrical connection to the base region. Such connection is often accomplished through the use of a large extrinsic base region, increasing the area of the base-collector P-N junction, and a large extrinsic base contact positioned close to the device surface.
U.S. Pat. No. 3,600,651 shows transistor structures wherein a polycrystalline layer is deposited on a masked semiconductor region. The result of this deposition is a monocrystalline region over the semiconductor material and contiguous polycrystalline regions over the masked, insulating material. Active device regions are then formed in the monocrystalline region, while device contacts are formed to the polycrystalline regions.
U.S. Pat. No. 4,483,726 shows a vertical, bipolar transistor wherein substrate silicon is oxidized to form isolating spacers between the device emitter and extrinsic base region/contact.
U.S. Pat. No. 4,428,111 shows a vertical, bipolar transistor wherein the layers forming the active base, collector and emitter regions are grown using molecular beam epitaxy (MBE). These layers are then processed to form the transistor, and device contacts made thereto.